Current demands for high density and performance associated with ultra large scale integration (ULSI) requires submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
As device features are increasingly miniaturized to increase the integration density, the need for effective isolation between individual devices becomes more critical. For the purpose of effective isolation between electrical devices, various isolation technologies have been introduced. An earlier method known as LOCOS (Local Oxidation of Silicon) was developed for MOSFET devices to prevent the establishment of parasitic channel between adjacent device. The LOCOS isolation technique involves the formation of an oxide bulk in the non-active area on the semiconductor substrate. The well-known drawbacks associated with LOCOS isolation are the formation of the so-called "bird's beak" oxide configuration and the associated encroachment of the field oxide beneath the oxidation mask.
As device dimensions reached submicron size, conventional LOCOS isolation technologies attained the limit of their effectiveness, and alternative isolation techniques were developed to increase the device density. One such isolation technology developed involves a process of creating trench structure during the integrated circuit fabrication. The utilization of trench structures to form isolation areas accomplished several major improvements such as prevention of latch-up and effective isolation of n-well regions from p-doped substrate in CMOS devices.
Typically, trench isolation involves etching a narrow, deep trench or groove in a silicon substrate and then filling the trench with a hard filling material such as silicon oxide. A problem with the use of hard materials is that they may cause dislocations and other defects in the silicon substrate during the subsequent thermal processes due to the differences in rates of thermal expansion between the filler material and the silicon substrate. For example, the trenches typically have contacts between a silicon substrate and silicon dioxide layers formed thereon. Because of the differing thermal coefficients of expansion of silicon and silicon dioxide, a stress problem from the mismatch occurs at the interface between the layers of silicon and silicon dioxide. This stress tends to cause undesirable damage in the silicon substrate near the trefich. Particularly, top edges of the trenches are susceptible to the generation of significant stress defects.
With this in mind, FIG. 1 depicts a cross-section of a portion of a prior art semiconductor device, which comprises a trench liner 12 formed on a silicon substrate 10. Conventionally, trench liner 12 is silicon dioxide formed by a conventional thermal oxidation process, i.e., at an oxidation temperature of 1050.degree. C. or less. During the thermal oxidation process to form silicon dioxide trench liner 12, oxidation stress is formed in interface region 14 within substrate 10 due to the different thermal expansion coefficients of silicon and silicon dioxide.
A trench isolation region 16 has been formed on trench liner 12 by filling the trench with oxide material, typically TEOS. The portion further includes a gate region 18 that is part of a field effect transistor having an active region 20, either a source or drain region, formed adjacent to trench isolation region 16 within substrate 10. Conductive silicide regions 22 have been formed on the top surface of active region 20 and gate region 18. A dielectric material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS) has been deposited over the substrate 10 to form an interlayer dielectric 24, and then the surface of interlayer dielectric 24 has been planarized. A local interconnection opening 26 has been formed by conventional etching processes, extending through dielectric layer 24 to silicide regions 22. Barrier layer 28 is then formed on the inner surface of local interconnect opening 22.
During the dielectric etching process to form local interconnection opening 22, it is desirable to stop the etching process at the silicide regions 22 formed on active region 20. However, it is often difficult to precisely stop the etching process at the silicide region 22. One reason is that the thermal oxidation process to form trench liner 12 causes undesirable stress defects in an interface region 14 between substrate 10 and trench liner 12, especially near the top edges of the trench isolation region 16. The stress defects in the interface region 14 make it difficult to precisely stop etching interlayer dielectric 24 at silicide region 22. This often causes local interconnect openings to extend through silicide region 22 to substrate 10, thereby-forming a dip 29 in the top surface of interface region 14. Upon filling local interconnect opening 26 with a conductive material to form a local interconnect line, a conductive path is undesirably created between the local interconnect line and substrate 10 through dip 29, thereby resulting in an intolerable amount of leakage current which decreases circuit performance, and in extreme circumstances, may cause failure of the circuit.
Thus, there is a need for a method that substantially reduces the stress defect at the top surface of an interface region between a substrate and a trench liner to prevent undesirable formation of a conductive path between the local interconnect line and the substrate.